The present invention relates generally to integrated circuit (IC) testing. More particularly, the present invention relates to translating test vectors from a first format suitable for use with a standalone IC tester into a second format suitable for use with an in-circuit tester, and vice versa.
During design and development, ICs, such as application specific ICs (ASICs), field programmable gate arrays (FPGAs), and so on, are routinely subjected to a series of tests, including standalone chip tests and in-circuit tests. A chip test typically tests all the logic within an individual IC using an input set of test vectors in a format suitable for use by the chip tester. One known chip tester is the Logic Master XL60, which is available from Integrated Measurement Systems. This tester uses, as input, a test file including test vectors in a proprietary format.
An in-circuit tester tests a completed printed circuit board assembly, which typically includes one or more ICs. The purpose of in-circuit testing is to verify that the assembly is free of manufacturing defects, such as solder shorts or opens, incorrect components, misoriented components, and so on. A typical in-circuit test assumes that the individual components that make up the assembly are defect free. The in-circuit tester uses a second set of test vectors in a format that differs, sometimes significantly, from the format of the test vectors used during chip testing. One such example is Hewlett-Packard Company""s pattern conversion format (PCF).
In-circuit testing is also commonly referred to as xe2x80x98bed-of-nailsxe2x80x99 testing. These nails make physical contact with routing traces on the printed circuit board, and can be used to drive stimuli to devices under test, and to receive responses to verify that all the device connections have been made. Typically, the stimuli used to test these device connections are generated programmatically from one of three types of files: 1) a device model for simple devices; 2) boundary scan device logic (BSDL) for large complicated devices with design-for-test; or 3) a device netlist for programmable devices. In all three cases an additional file that represents the printed circuit boards""s topology or connection order is used to generate tests for each device.
The process described above is a common way to generate in-circuit tests for such devices. In some cases, however, the necessary inputs do not exist. For example, older chips that were designed before boundary scan was popular were too complicated to be represented by a model, and most likely used a non-standard netlist format. Quite often, modern designs have this same problem, as short cuts are taken to save time or money. Generating in-circuit tests for these devices has posed a unique challenge. In many cases the solution has been simply not to test the device once the assembly is complete. Obviously, this can create reliability and system test yield problems.
Typically, millions of test vectors must be developed to test an IC at the chip test level. Many thousands of these represent connections that will be tested again during in-circuit testing. Consequently, once a chip test has been successfully conducted, and the test vectors have been proven, it would be desirable to reuse as much as possible of this subset of test vectors in conducting the in-circuit test. Because of the very different formats required by the above-described chip test and in-circuit test tools, however, this subset is frequently unusable. Similarly, if an in-circuit test fails, it is sometimes necessary to verify that the test vectors being used for the in-circuit test are accurate. Under such circumstances, it would be desirable to use the in-circuit test vectors in a standalone chip test to determine whether the fault is due to the chip, or to the in-circuit test vectors. Again, due to the varying formats of the two sets of test vectors, the in-circuit test vectors frequently cannot be used in the chip test environment.
U.S. Pat. No. 5,778,004, issued in the names of Jennion, et al. (xe2x80x9cJennion ""004xe2x80x9d), discloses an IC test environment which includes at least two test configurations where each test configuration employs a different test vector format. Jennion ""004 discloses apparatus and methods for translating a first set of test vectors having a first format used in a first test configuration into a second set of test vectors in a second format to be used in a second test configuration. The system disclosed therein includes means for receiving user selections representing at least one of a desired set of signals and a desired range of test vectors to be processed from the first set of test vectors; means for extracting data related to the user selections from the first set of test vectors; and means for converting the extracted data into the second set of test vectors in the second format.
The prior art does not seem to disclose a vector translator that provides a method for translating test vectors from a format suitable for use with a chip tester (such as the XL60 format) into a format suitable for use with an in-circuit tester, and vice versa. Thus, there is a need in the art for such a vector translator.
The present invention satisfies these needs in the art by providing apparatus and methods for translating test vectors from a format suitable for use with a chip tester into a format suitable for use with an in-circuit tester, as well as apparatus and methods for translating test vectors from a format suitable for use with an in-circuit tester into a format suitable for use with a chip tester.
Methods for translating test vectors from a format suitable for use with an integrated circuit tester into a format suitable for use with an in-circuit tester include providing a first test file in a first format that is suitable for use with the integrated circuit tester for standalone testing of an integrated circuit. The first test file is then translated into a second test file in a second format. The second format is suitable for use with the in-circuit tester for in-circuit testing of the integrated circuit. Preferably, the format of the first file is IMS format and file includes a set of test vectors for standalone testing of the integrated circuit, as well as a set of pin definitions that define pins of the integrated circuit. The format of the second file is preferably PCF.
The first test file can be provided, at least in part, by providing a complete test file that includes test vectors for testing logic within the integrated circuit, and selecting a subset of the test vectors included in the complete test file. The selected subset can then be included in the first test file. The first test file can be translated into the second test file by identifying in the first file test vector data in the first format, and writing to the second file test vector data in the second format that corresponds to the test vector data in the first format. The translation can also include identifying in the first file pin information in the first format. Based on the pin information, pin assignment statements, pin definitions, and pin functionality statements can be written to the second file in the second format.
Similarly, methods for translating test vectors from a format suitable for use with an in-circuit tester into a format suitable for use with an integrated circuit tester include providing a first test file in a first format that is suitable for use with the in-circuit tester for in-circuit testing of an integrated circuit. The first test file is then translated into a second test file in a second format. The second format is suitable for use with the integrated circuit tester for standalone testing of the integrated circuit. Preferably, the first file is in PCF, and the second file is in IMS format.
Apparatus according to the invention include computer-readable media having stored thereon computer-executable instructions for performing these methods.
The methods and apparatus of the present invention can be used in a test evaluation method to verify that a device being subjected to an in-circuit test is not flawed. The test evaluation method comprises performing an in-circuit test on a device under test (DUT) using an in-circuit test file in a format suitable for input into an in-circuit tester. If the DUT fails the in-circuit test, then the in-circuit test file is translated into an integrated circuit test file in a format that is suitable for input into a standalone integrated circuit tester. A standalone integrated circuit test is performed on a golden device using the integrated circuit test file. A golden device is a device of the kind under test that has been proven to work properly. If the golden device passes the standalone integrated circuit test, then it can be reasonably concluded that the DUT is not flawed. The invention thus provides a mechanism for verifying (with a reasonable degree of certainty) that a DUT is not flawed despite the fact that it may have failed an in-circuit test. This could indicate that, for example, the circuit board itself is flawed. Other aspects of the present invention are described below. If the golden device fails the standalone integrated circuit test, then it can be reasonably concluded that the in-circuit test file is flawed, or that the in-circuit test file introduced certain tests that were not conducted during previous standalone integrated circuit testing on the golden device.